MPC8540 datasheet(596/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-92

Freescale Semiconductor

Local Bus Controller

13.5.4.3 SDRAM Machine Limitations

This section describes limitations of the local bus SDRAM machine.

13.5.4.3.1 Analysis of Maximum Row Number Due to Bank Select

Multiplexing

LSDMR[BSMA] is used to multiplex the bank select address. The BSMA field and corresponding

multiplexed address are shown below:

000 LA12–LA13

001 LA13–LA14

…

111 LA19–LA20

Note that LA12 is the latched value of LAD12.

The highest address pins that the bank selects can be multiplexed with are LA[12:13], which limits

the pins for the row address to LA[14:31]. For a 32-bit port, the maximum width of the local bus,

LA[30:31] are not connected, and the maximum row is LA[14:29]. The local bus SDRAM

machine supports 15 rows, which is sufficient for all devices.

13.5.4.3.2 Bank Select Signals

Page-based interleaving allows bank signals to be multiplexed to the higher-order address pins to

leave room for future upgrades. For example, a user could multiplex the bank select signals to

LA[14:15], leaving LA16 to connect to the address pin for a larger memory size.

This allows the system designer to design one board that can be used with a current generation of

SDRAM devices and upgraded to the next generation without requiring a new board layout.

13.5.4.3.3 128-Mbyte SDRAM

Figure 13-74 shows the connection to an SDRAM of 128 Mbytes. Note that all circuit diagrams

are principal connection diagrams and do not show any means of signal integrity.

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