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MPC8540 Datasheet(PDF) 599 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 599 Page - Freescale Semiconductor, Inc |
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599 / 1302 page ![]() Initialization/Application Information MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 13-95 13.5.4.3.4 256-Mbyte SDRAM This example uses the same Micron SDRAM as in the previous example, but doubles the number of devices connected and therefore uses two chip selects. 13.5.4.3.5 512-Mbyte SDRAM This example uses the MT48LC64M4A2FB from Micron to implement 512 Mbytes. In this SDRAM organization: • The 32-bit port size is 8 × 4 × 64 Mbit × 2 chip select lines. • Each device has 4 internal banks, 13 row address lines, and 11 column address lines. Table 13-39. Register Settings for 128-Mbytes SDRAMs Register Field Value BRn BA Base address XBA Ext. Base Address PS 11 = 32-bit port size MS 011 = SDRAM-local bus V1 ORn AM 11_1111_1000_0000_0000_0 XAM 11 COLS 011 ROWS 100 LSDMR RFEN 1 OP 000 BSMA 011 RFRC From device data sheet PRETOACT From device data sheet ACTTOROW From device data sheet BL 0 WRC From device data sheet BUFCMD 0 CL From device data sheet |
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