MPC8540 datasheet(602/1302 Pages) FREESCALE

602 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-98

Freescale Semiconductor

Local Bus Controller

self-refresh command to the SDRAM. The LBC applies the same timing as for the auto refresh,

but also pulls the SDRAM CKE (LCKE) signal low in the same cycle. This can only be done with

all banks being idle; the SDRAM machine must precharge them ahead of this. As long as CKE

stays low, the device refreshes itself and does not need to see any refreshes from the local bus. To

exit self refresh, CKE simply has to be pulled high. Note that after returning from self-refresh

mode the SDRAM needs a supplier-specific time before it can accept new commands and the

auto-refresh mechanism has to be started again. Figure 13-76 shows this timing. The SDRAM

controller always uses 200 local bus clocks, which should satisfy any SDRAM requirements. As

in the case of the power-down mode, the figure does not show the precharge-all command that is

issued by the LBC automatically prior to the self-refresh command.

Refer to Section 13.4.3.3, “Intel PC133 and JEDEC-Standard SDRAM Interface Commands,” for

SDRAM interface commands and information on the self-refresh command.

Figure 13-76. SDRAM Self-Refresh Mode Timing

EXTERNAL CK

CKE

Supplier-specific

minimum time

New command

can occur here

Self-refresh exit

Self-refresh entry

All banks idle

NOP

Stable clock

MPC8540 Datasheet(PDF) 602 Page - Freescale Semiconductor, Inc