MPC8540 datasheet(601/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-97

13.5.4.3.6 Power-Down Mode

SDRAMs offer a power-down mode during which the device is not refreshed, and therefore, data

is not maintained. This mode is invoked by driving CKE low, while all internal banks are idle; note

that they must be precharged first. Figure 13-75 shows the timing. Note that the figure does not

show the precharge-all command that is issued by the LBC automatically prior to the self-refresh

command.

Figure 13-75. SDRAM Power-Down Timing

CKE remains low, as long as the device is powered down. After CKE transitions to high, the

SDRAM exits the power-down mode.

13.5.4.3.7 Self-Refresh

In order to be able to stop activity on the local bus (for power save or debug), while the content of

the SDRAM is maintained, the self-refresh mode is supported. This mode is invoked by issuing a

PSDMR

RFEN

000

BSMA

011

RFRC

From device data sheet

PRETOACT

From device data sheet

ACTTOROW

From device data sheet

WRC

From device data sheet

BUFCMD

From device data sheet

Table 13-43. Register Settings for 512-Mbyte SDRAMs (continued)

Field

Value

COMMAND

CKE

NOP

Supplier specific

minimum time

New command

accepted here

All banks idle

Cannot violate minimum

refresh specification

(As defined by

S, RE, CE, W,

& ADDR)

Clock low-to-high transitions

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