MPC8540 datasheet(605/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-101

13.5.4.4

Parity Support for SDRAM

Contrary to older DRAM technologies, SDRAM devices typically are organized either x4, x8, x16

or x32. There are no mainstream devices that include parity support. To allow for error protection

on the local bus an additional SDRAM for the 4 parity bits must be used. Since the local bus allows

for SDRAM accesses with less than the full port size, read-modify-write cycles are supported for

SDRAM write cycles.

Figure 13-78 shows a connection diagram.

Figure 13-78. Parity Support for SDRAM

13.5.5 Interfacing to ZBT SRAM

In many applications, SDRAM provides sufficient performance for the local bus. However,

especially in networking applications, memory access patterns are often random and SDRAM is

not optimized for that case. ZBT SRAMs have been designed to optimize the performance in

networking applications. This section describes how to interface to ZBT SRAMs. Figure 13-79

• • •

×4

DP[0:3]

• • •

DATA[0:7]

DATA[24:31]

LCSn

LSDWE

LAD[0:31]

LSDRAS

LALE

LCLK

LCKE

LSDCAS

Latch

DQM0

DQM3

LSDDQM[0:3]

Local Bus Interface

CAS

32M

× 8

RAS

BA[1:0]

DQM

CKE

CLK

ADDR[12:0]

SDRAM

DQ[0:7]

LSDA10

A10

CAS

32M

× 4

RAS

BA[1:0]

DQM

CKE

CLK

ADDR[12:0]

SDRAM

DQ[0:3]

A10

CAS

32M

× 8

RAS

BA[1:0]

DQM

CKE

CLK

ADDR[12:0]

SDRAM

DQ[0:7]

A10

LDP[0:3]

LPBSE

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