MPC8540 datasheet(607/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-103

The UPM also supports single beat accesses. Because the ZBT SRAM does not support this and

always responds with a burst, the UPM pattern has to take care that data for the critical beat is

provided (for write) or sampled (for read), and that the rest of the burst is ignored (by negating

WE). The UPM controller basically has to wait for the end of the SRAM burst to avoid bus

contention with further bus activities.

ZBT SRAMs have a power down mode, which is invoked by the ZZ pin. Connecting a GPIO pin

to ZZ allows use of that power down mode; however accesses to the SRAM while in power down

mode do not create valid results. This should be taken care of by the system software.

Another observation is that SRAMs are available with natural parity. In the example, we use a

×18

SRAM, which holds two data bytes and two parity bits. While for the support of parity on SDRAM

banks the local bus has to use read-modify-write cycles and compromise performance, SRAM

banks can be used with natural parity and do not compromise performance for parity support.

13.5.6 Interfacing to DSP Host Ports

In many applications, an integrated communications processor aggregates traffic for DSPs and

distributes that traffic to the DSPs. The local bus allows connection to a variety of different DSP

host ports and this section gives some information on how to interface to some example DSPs.

13.5.6.1

Interfacing to MSC8101 HDI16

This section describes how to interface to the HDI16 peripheral interface of the MSC8101. After

initial set-up of the interface, the host and HDI16 device can communicate either by a read and

write transaction from the core or, if the setup on the DSP and the host are implemented

appropriately, by DMA transfers of the host DMA controller, which can be triggered automatically

by signals generated by the HDI16 peripheral.

13.5.6.1.1 HDI16 Peripherals

The host interface (HDI16) is a 16-bit-wide, full-duplex, double-buffered parallel port that can

directly connect to the data bus of a host processor. It supports a variety of buses and gluelessly

connects with a number of industry-standard microcomputers, microprocessors, and DSPs. The

HDI16 also supports the 8-bit host data bus, which makes it fully compatible with the DSP56300

HI08 (as viewed by the host side, not from the DSP side).

The host bus can operate asynchronously to the SC140 core clock, and the HDI16 registers are

divided into two banks. The host register bank is accessible to the external host, and the core

The MSC8101HDI16 host port peripheral has two sets of 16-bit-wide registers—one set is only

visible internally to the DSP, while the other set is visible only to the external host processor.

Figure 13-81 illustrates the relationship between the two sides.

MPC8540 Datasheet(PDF) 607 Page - Freescale Semiconductor, Inc