MPC8540 datasheet(611/1302 Pages) FREESCALE

611 / 1302 page

Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-107

access to the interface for all 16 transactions within that burst. By using the addressing as defined,

if the first access is at 0x20, the last will be at 0x3e but, more importantly, the four host Tx/Rx

registers will have been looped around four times.

13.5.6.1.4 Host 60x Bus: HDI16 Peripheral Interface Hardware Timings

The host UPM–controlled local bus and the HDI16 MSC8101’s HDI16 host interface are both

programmable. Careful programming of the host chip select registers and UPM can meet the

HDI16 MSC8101 host port timings.

On any bus access the critical timing for both read and write is typically around the data latch

point. For the UPM based read access, the host has the flexibility to latch data on a rising or falling

LCLK edge. The falling LCLK edge is used here to latch the HDI16 data into the host MSC8101

at its earliest convenience.

After the data is latched, appropriate HDI16 port data hold time is ensured before the data strobe

(DS) and chip select (CS1) are negated.

On a UPM write cycle, the critical action is in enveloping the DS assertion with CS asserted to

ensure proper write data hold time after latching by the HDI16 host port.

Special attention needs to be given to both the host read and write access strobe (DS) negation

times (HDS assert).

The HDI16 MSC8101 specifies some restrictions for consecutive register access, which results in

a hold off negation time for the read and write access strobes.

Rather than restrict the firmware to avoid consecutive bus accesses to host port registers, the

negation hold off times should be accommodated in the UPM hardware interface settings.

Additional clocks must be built into the end of UPM based cycle giving appropriate time before

the next bus cycle starts.

The timings can be readily adapted to allow external decode logic to be added to support chip

selects for a larger number of DSP HDI16 host ports.

13.5.6.2

Interfacing to MSC8102 DSI

The MSC8102 direct-slave interface (DSI) gives an external host direct access to the MSC8102.

It provides the following slave interfaces to an external host:

•

Asynchronous SRAM-like interface giving the host single accesses (with no external

clock).

•

Synchronous SSRAM-like interface giving the host single or burst accesses of 256 bits

(eight beats of 32 bits or four beats of 64 bits) with its external clock decoupled from the

MSC8102 internal bus clock.

MPC8540 Datasheet(PDF) 611 Page - Freescale Semiconductor, Inc