MPC8540 datasheet(615/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-111

DSI expects the host to react within one clock cycle, some tricks can be implemented to support

the synchronous mode.

HTA drives LUPWAIT of the UPM. MxMR[UWPL] must be cleared to interpret the correct

polarity of HTA. Because this signal influences the internal state machine of the local bus clock,

the local bus cannot react to HTA changes correctly within one local bus clock. Refer to

Section 13.4.4.4.10, “Wait Mechanism (WAEN),” for more detailed information.

The solution to this lies in that the local bus operates at a higher frequency than the DSI interface

of the DSP. The local bus clock can be divided by an integer divider (1:2, 1:3 or 1:4) to generate

the DSI clock. This should not be a problem because the local bus is designed for much higher

frequencies than the DSI. Because all timings are given in DSP DSI clock cycles, the UPM

patterns must be adjusted appropriately and need to assert a signal for 2, 3 or 4 clocks (as many as

the divider ratio) instead of one. Fortunately, the UPM has the REDO feature, which allows every

UPM RAM entry to be executed 1

×, 2×, 3× or 4×, which should be sufficient for any divider ratio

that would be used in this case.

Figure 13-85. Interface to MSC8102 DSI in Synchronous Mode

This solution allows the local bus to react within multiple local bus clocks to the HTA signal and

be still within one DSI clock. Typically, LUPWAIT is synchronized internally, and only 2 clocks

after LUPWAIT changes, new data can be sampled or presented. For example, if the local bus

HWBS/HDBS/

HWBE/HDBE[0:3]

HD[0:31]

HA[11:26]

Latch

HCID[0:3]

HA[27:29]

HRDS/HRDE

HINT

HBRST

HBCS

HCS

MSC8102

Local Bus Interface

LAD[0:31]

LALE

LA[27:29]

LGPL2

LBS[0:3]

INTn

LGPLn

LCSn

LCSy

HCLKIN

HTA

Clock

LCLK

LUPWAIT

LGPLy

divider

Sync

logic

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