MPC8540 datasheet(612/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-108

Freescale Semiconductor

Local Bus Controller

The DSI supports 32- or 64-bit data bus. For connection to the local bus the DSI has to be

configured in 32-bit mode. This is achieved through the DSP reset configuration.

The DSI supports two addressing modes, which are determined during the MSC8102 boot

sequence. Refer to details in the MSC8102 documentation.

•

Full address bus mode with HA[11:29] used in both 32-bit data mode and 64-bit data mode

•

Sliding window mode with HA[14:29] used in both 32-bit data mode and 64-bit data mode

13.5.6.2.1 DSI in Asynchronous SRAM-Like Mode

The local bus supports the DSI single strobe as well as the DSI double strobes of operation. As an

example the dual strobe configuration is shown below.

Figure 13-82 shows the interface to the MSC8102 DSI for asynchronous mode.

Figure 13-82. Interface to MSC8102 DSI in Asynchronous Mode

The asynchronous SRAM-like mode of the DSI is inherently slower than the synchronous mode

and should be used, if only relatively small amounts of data are transferred between the

communications controller and the MSC8102. To allow for maximum timing flexibility, the UPM

machine of the LBC should be used.

The UPM programmer is responsible for ensuring correct setup and hold timings for all signals.

The UPM allows sufficient control to satisfy any requirements here.

Figure 13-83 shows an asynchronous write access. The DSI samples the host chip ID signals

(HCID[0:3]) on the first falling edge of the host write byte strobe signals (HWBS) on which the

host chip select signal (HCS) is asserted. If the HCID[0:3] signals match the CHIPID value, the

HWBS/HDBS/

HWBE/HDBE[0:3]

HD[0:31]

HA[11:26]

Latch

HCID[0:3]

HA[27:29]

HRDS/HRDE

HTA

HINT

HBCS

HCS

MSC8102

Local Bus Interface

LAD[0:31]

LALE

LA[27:29]

LGPL2

LBS[0:3]

LUPWAIT

INTn

LCSn

LCSy

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