MPC8540 datasheet(614/1302 Pages) FREESCALE

614 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-110

Freescale Semiconductor

Local Bus Controller

(HD) and terminate the access by negating HRDS. If the data for this access is already in the read

buffer due to the prefetch mechanism, assertion time of HTA is improved. The WAEN feature of

the UPM must be used to insert wait states while the DSI is busy. MxMR[UWPL] has to be cleared

to interpret the correct polarity of the HTA signal.

Because the UPM is used in the mode, the DCR[4]:HTAAD should be set to 1 and the drive time

control field, DCR[9–10]:HTADT, should be defined to a value different than 00. This mode is

specially designed to be used for implementations with a pull-up resistor on HTA.

The host can start its next access (back-to-back accesses) without negating the HCS signal

between accesses. If the next access is not to the same MSC8102, then to prevent contention on

HTA, the host must wait until the previous DSI stops driving HTA before it accesses the next

device. If the next access is to the same MSC8102, the host must not start consecutive access

before HTA is actively driven to 1 by the previous access. The easiest way to achieve this is to

insert idle cycles at the end of the UPM pattern to guarantee that HTA is inactive.

Figure 13-84. Asynchronous Read from MSC8102 DSI

13.5.6.2.2 DSI in Synchronous Mode

The synchronous SSRAM-like mode of the DSI is inherently faster than the asynchronous mode

and should be used if larger amounts of data are transferred between the communications

controller and the MSC8102. This will optimize the bus utilization, especially if several

MSC8102s are connected to one local bus. The UPM machine of the LBC must be used to

implement this interface.

Figure 13-85 shows the interface for synchronous mode. Because the DSI will assert and negate

HTA in synchronous mode even within a burst transfer on a clock-by-clock basis and because the

HCS

HCID[0:3]

HA[11:29]

HDST[0:1]

HD[0:63]

HWBS[0:7]

HRDS

HTA

Legend:

Timing conventions:

Valid value that can be 1 or 0

Don’t care

Three-state output signal that is not driven by the DSI

HTAAD = 0 & HTADT = 00

HTAAD = 1 & HTADT = 01,10,11

MPC8540 Datasheet(PDF) 614 Page - Freescale Semiconductor, Inc