MPC8540 datasheet(618/1302 Pages) FREESCALE

618 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-114

Freescale Semiconductor

Local Bus Controller

Synchronous Single Write

Figure 13-87 shows a synchronous single write access.

Figure 13-87. Synchronous Single Write to MSC8102 DSI

The DSI samples HA, HDST, HCID, HD, HWBE, HRDE, and HBRST on the first HCLKIN rising

edge on which HCS is asserted. If HCID[0:3] match the CHIPID value, the DSI is accessed. At

least one HWBE signal is asserted, and HRDE and HBRST are negated. Assertion of HTA

indicates that the DSI is ready to complete the current access and the host must terminate this

access. Because HTA is connected to the LUPWAIT signal of the UPM, all local bus signals are

frozen until HTA goes to 0 and then the UPM continues in its pattern. Typically, HTA is asserted

immediately. If the write buffer is full, HTA assertion is delayed. HTA is asserted for one HCLKIN

cycle, driven to logic 1 in the next cycle, and stops being driven on the next rising edge of

HCLKIN. The host can start its next access to the same MSC8102 immediately on the next

HCLKIN rising edge without negating HCS between accesses. If the next access is not to the same

MSC8102, then, to prevent contention on HTA, the host must wait to access the next device until

the previous DSI stops driving HTA. The easiest way to achieve this is to insert idle cycles at the

end of the UPM pattern to guarantee that HTA is inactive.

HCLKIN

HCS

HCID[0:3]

HA[11:29]

HDST[0:1]

HD[0:63]

HWBE[0:7]

HRDE

HBRST

HTA

Legend:

Timing conventions:

Valid value that can be 1 or 0

Don’t care

Three-state output signal that is not driven by the DSI

MPC8540 Datasheet(PDF) 618 Page - Freescale Semiconductor, Inc