MPC8540 datasheet(619/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-115

Synchronous Single Read

Figure 13-88 shows a synchronous single read access.

Figure 13-88. Synchronous Single Read from MSC8102 DSI

The DSI samples HA, HDST, HCID, HWBE, HRDE, and HBRST on the first HCLKIN rising

edge on which HCS is asserted. If the HCID[0:3] signals match the CHIPID value, the DSI is

accessed. HRDE is asserted, and HWBE and HBRST are negated. If DCR[8]:RPE is set (see

MSC8102 documentation), read access to the memory space (not to the register space) initiates

prefetching data from consecutive addresses in the internal memory space. Assertion of HTA

indicates that data is valid and the host must sample the HD and terminate the access. Because

HTA is connected to the UPM LUPWAIT signal, all local bus signals are frozen until HTA goes

to 0; then the UPM continues in its pattern. HTA is asserted earlier when the data for this access

is already prefetched to the read buffer. It asserted for one HCLKIN cycle and driven to logic 1 in

the next cycle. It stops being driven on the next rising edge of HCLKIN. The host can start its next

access to the same MSC8102 immediately in the next HCLKIN rising edge without negating HCS

between accesses. If the next access is not to the same MSC8102, then, to prevent contention on

HTA, the host must wait to access the next device until the previous DSI stops driving HTA. The

easiest way to achieve this is to insert idle cycles at the end of the UPM pattern to guarantee that

HTA is inactive.

HCLKIN

HCS

HCID[0:3]

HA[11:29]

HDST[0:1]

HD[0:63]

HWBE[0:7]

HRDE

HBRST

HTA

Legend:

Timing conventions:

Valid value that can be 1 or 0

Don’t care

Three-state output signal that is not driven by the DSI

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