MPC8540 datasheet(616/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-112

Freescale Semiconductor

Local Bus Controller

clock ratio is 3

× the DSI clock, data can be sampled in the third local bus sub-clock, which is the

last third of the DSI clock. If the local bus clock ratio is only 2

× the DSI clock, there is a special

mode, where the LUPWAIT is NOT synchronized. Refer to Section 13.4.4.5, “Synchronous

Sampling of LUPWAIT for Early Transfer Acknowledge,” for more detailed information. In this

mode, data is sampled in the 2nd subclock, which is the second half of the DSI clock. AC timing

of LUPWAIT must be met in this mode; otherwise indeterministic behavior may occur.

The remaining issue is the synchronization of the UPM cycles to the beginning of the DSI clock

cycle. Because the UPM executes n cycles for every cycle of the DSI, a mechanism must be used

to ensure that the UPM changes transitions in a way that is synchronized to the DSI clock. The

solution is to use a special synchronize cycle at the beginning of the pattern. A GPL signal is used

to control a multiplexer and to activate external synchronization logic, which uses the DSI clock

to stall the UPM by asserting LUPWAIT until the beginning of the next DSI cycle. After that, this

GPL signal must be negated and the multiplexer connects LUPWAIT to HTA instead, for the rest

of the bus cycle. Note that the GPL signals should be used in the inverted state of their inactive

state (GPL[0:4] are 1 when inactive, GPL5 is 0 when inactive) to start the synchronization process.

Figure 13-86 shows an example for a synchronization mechanism for a clock divider of 3. Note

that the length of the synchronization cycle depends on the relative start of the synchronization

process and varies with every access. It can vary in length from one to n (clock ratio) local bus

clocks.

The second column (compensation cycle) is intended to compensate for the reaction time of

LUPWAIT to get in lockstep with the DSI clock. For example, if the clock divider ratio is 1:3 and

the LUPWAIT reaction time is two local bus clocks, because LUPWAIT is synchronized, then one

local bus clock should be inserted.

Figure 13-86. UPM Synchronization Cycle

Table 13-47. UPM Synchronization Cycles

Sync CYCLE

Compensation CYCLE

DSI CYCLE 1

Bits

cst1–cst4

0–3

bst1–bst4

4–7

g0xx

8–11

g1tx

12–13

LCLK

DSI_CLK

LGPLy

LUPWAIT

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