MPC8540 datasheet(613/1302 Pages) FREESCALE

613 / 1302 page

Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-109

DSI is accessed. The DSI will signal with the assertion of the host transfer acknowledge signal

(HTA), whether it is ready to sample the host data bus (HD), and the host can terminate the access

by immediately negating HWBS. The WAEN feature of the UPM must be used to insert wait states

while the DSI is busy. The UWPL bit in the MxMR must be cleared to interpret the correct polarity

of HTA. The DSI samples the host address bus (HA) and the host data bus (HD) on the rising edge

of HWBS. In addition the assertion of HWBS[0:3] are sampled at the end and are part of the access

attributes.

Because the UPM is used for this mode, the DCR[4]:HTAAD should be set to 1 and

DCR[9–10]:HTADT should be defined to a value different than 00. This mode is to be used in

implementations with a pull-up resistor on HTA. The host can start its next access (back-to-back

accesses) without negating HCS between accesses. If the next access is not to the same MSC8102,

then to prevent contention on the HTA signal, the host must wait until the previous DSI stops

driving HTA before it accesses the next device. If the next access is to the same MSC8102, the

host must not start consecutive accesses before HTA is actively driven to a value of 1 by the

previous access. The easiest way to achieve this is to insert idle cycles at the end of the UPM

pattern to guarantee that HTA is inactive.

Figure 13-83. Asynchronous Write to MSC8102 DSI

Figure 13-84 shows an asynchronous read access. The DSI samples the host address bus (HA) and

the HCID on the first falling edge of the host read strobe signal (HRDS) on which the HCS is

asserted. If HCID[0:3] match the CHIPID value, the DSI is accessed. When the DCR[8]:RPE bit

is set, read access to the memory space (not to the register space) initiates data prefetching from

consecutive addresses in the internal memory space. The DSI signals (with the assertion of the host

transfer acknowledge signal (HTA)) that data is valid, and the host can sample the host data bus

HCS

HCID[0:3]

HA[11:29]

HDST[0:1]

HD[0:63]

HWBS[0:7]

HRDS

HTA

Legend:

Timing conventions:

Valid value that can be 1 or 0

Don’t care

Three-state output signal that is not driven by the DSI

HTAAD=0 & HTADT=00

HTAAD=1 & HTADT=01,10,11

MPC8540 Datasheet(PDF) 613 Page - Freescale Semiconductor, Inc

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