MPC8540 datasheet(610/1302 Pages) FREESCALE

610 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-106

Freescale Semiconductor

Local Bus Controller

The connections are specified as follows:

•

One chip select, LCSn (whatever is available in the system), is used to memory map

accesses from the host local bus to the HDI16 MSC8101’s HDI16 peripheral, and is

connected to the HDI16 chip select line (HCS).

•

This interface uses two separate general-purpose strobe lines (LGPL1 and LGPLy):

— LGPL1 is programmed to generate the HDI16 read/write signal (HRDRW), which is

typically high for a read access and low for write access. In any case, the host port

requires a HR/W signal. This can be generated by using LGPL1, and allows it to adopt

the timing virtually without restrictions. Alternatively the designer can invert LBCTL

to generate this signal. It is the responsibility of the UPM pattern designer to plan for

the additional delay of that inverter in the UPM pattern to satisfy the AC timings at the

DSP host port.

— LGPLy is programmed to generate the HDI16 data strobe (HDS), which must be

asserted every 16-bit read or write transaction.

•

Data lines—The bus data lines (LADn) are directly connected to the HDI16 data lines

(HDn).

•

DMA request/Service request signals (HRRQ & HTRQ)—as appropriate in the application

•

Address lines—The address lines between the LBC and the HDI16 MSC8101 can either be

connected in a straightforward or a specific manner to enable burst transfers across the

HDI16. The connections are defined as follows and are described in more detail in the

following sub-section:

— Either LA[27] or latched value of A25 -> HA0

— Either LA[28] or latched value of A26 -> HA1

— LA[29] -> HA2

— LA[30] -> HA3

•

Ground lines—In order to provide the best ground plane, it is highly advised that all

grounds are common and connected together.

13.5.6.1.3 Supporting Burst Transfers

As mentioned previously, to facilitate burst transfers the host’s local bus address lines can be

connected in a very specific way. First, the local bus A31 signal is not required, as the HDI16

registers are 16-bit word addressed. Secondly, local bus LA[27] and LA[28] signals can be

eliminated, so that the host side transmit and receive registers wrap around the same four 16-bit

word addresses.

For example, host transmit register 0 on the HDI16 peripheral (address 0x04) can be obtained by

the host by accessing any of the following memory mapped addresses: 0x20, 0x28, 0x30, or 0x38.

This is critical for burst accesses as the source or destination addresses increment after each 16-bit

MPC8540 Datasheet(PDF) 610 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 610 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL