MPC8540 datasheet(606/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-102

Freescale Semiconductor

Local Bus Controller

shows the connections. The UPM is used to generate control signals. The same interfacing is used

for pipelined and flow-through versions of ZBT SRAMs. However different UPM patterns must

be generated for those cases. Because ZBT SRAMs will mostly be used by performance-critical

applications, we assume here that, typically, the maximum width of the local bus of 32 bits will be

used.

ZBT SRAMs allow different configurations. For the local bus the burst order should be set to

linear burst order by tying the mode pin to GND; CKE should also be tied to ground.

ZBT SRAMs perform four-beat bursts. Because the LBC generates eight-beat transactions (for 32

bit ports) the UPM breaks down each burst into two consecutive four-beat bursts. The internal

address generator of the LBC generates the new A27 for the second burst.

Figure 13-79. Interface to ZBT SRAM

Because we use linear burst on the SRAM, the device will itself burst with the burst addresses of

[0:1:2:3]. The local bus always generates linear bursts and expects [0:1:2:3:4:5:6:7]. Therefore,

two consecutive linear bursts of the ZBT SRAM with A27 = 0 for the first burst and A27 = 1 for

the second burst give the desired burst pattern.

DP[2:3]

DATA[0:15]

DATA[16:31]

BW[0:1]

BW[2:3]

DP[0:1]

× 18

ADV/LD

BW[0:1]

MODE

CKE

CLK

SA[19:0]

ZBT

DQ[0:17]

SRAM

× 18

ADV/LD

BW[0:1]

MODE

CKE

CLK

SA[19:0]

ZBT

DQ[0:17]

SRAM

LBS[0:3]

LCSn

LGPL0

LGPL2

LAD[0:31]

LGPL1

Local Bus Interface

LALE

LDP[0:3]

LCLK

GPIO

LA[27:29]

Latch

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