MPC8540 datasheet(604/1302 Pages) FREESCALE

604 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-100

Freescale Semiconductor

Local Bus Controller

Clock skew (time of flight): clock skew between the LBC and the clock at the memory device. The

local bus DLL feedback mechanism must be used to control this skew to optimize the timing

margins, as described in the rest of this subsection.

Address setup margin = cycle time – local bus address CTQ – SDRAM address input setup time

– address TOF + clock skew

Address hold margin = local bus address output hold time + address TOF – SDRAM address input

hold time – clock skew

Data write to SDRAM setup margin = cycle time – local bus data CTQ – SDRAM data input setup

time – data TOF + clock skew

Data write to SDRAM hold margin = local bus data output hold time + data TOF – SDRAM data

input hold time – clock skew

Data read from SDRAM setup margin = cycle time – SDRAM data CTQ – local bus data input

setup time – data TOF – clock skew

Data read from SDRAM hold margin = SDRAM data output hold time + data TOF – local bus data

input hold time + clock skew

To improve the timing margins a DLL is used to generate external clocks, which minimize the

skew between the local bus and the memory clock. Figure 13-77 shows relative timings for the

local bus clock DLL.

Figure 13-77. Local Bus DLL Operation

tD = tDLL+tP

RBC (reference bus clock)

LSYNC_OUT

LSYNC_IN

LCLK

LBC output signals on pins

MPC8540 Datasheet(PDF) 604 Page - Freescale Semiconductor, Inc