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MPC8540 Datasheet(PDF) 608 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 608 Page - Freescale Semiconductor, Inc |
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608 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 13-104 Freescale Semiconductor Local Bus Controller All of the HDI16 peripheral’s registers are mapped directly onto the MSC8101’s QBus, as defined by the MSC8101 16-bit Digital Signal Processor Reference Manual (order number MSC8101RM); the transmit and receive FIFOs are mapped onto the DMA data bus such that the DMA controller can access them directly without core intervention. The addressing for each of these registers is defined in Section 13.5.6.1.2, “Physical Interconnections.” The HDI16 host port itself is a 16-bit-wide parallel port with various strobe and multiplexing options. The most important HDI16 host port facet is that it is specified as an asynchronous interface and so reduces concerns over clock skew between the HDI16 host port and the host device’s buses. Furthermore, with all the host port registers being accessed with a single chip select and four address lines, as far as the local bus is concerned, the DSP host port is akin to an asynchronous memory mapped region. So, for the HDI16 port in single strobe mode, the host device asserts a chip select, a single data strobe and a read/write line to select HDI16 read or write bus operations. The read and write strobes are also used as the data latch control to complete the bus transactions, obviating the need for any handshake termination signal from the DSP. The UPM programmer is responsible for satisfying the AC timings of the HDI16 transactions. Through appropriate mode selection, the HDI16 peripheral’s feature set can be fully supported by the local bus’s UPM controlled signals. The UPM defined interface can be used with any of the local bus’s eight chip selects to give the 16-bit port size and strobe generation that matches that of the HDI16 host port. Figure 13-80 shows the internal register diagram of the HDI16. Figure 13-80. MSC8101 HDI16 Peripheral Registers TX0 TX1 TX2 TX3 HORX HCR HSR HCVR HPCR RX0 RX1 RX2 RX3 16 16 16 16 HOTX ISR ICR CVR 16 16 16 64 64 QBus Data Bus DMA Data Bus Host Bus 16 16 16 16 16 16 16 16 64 64 |
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