Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

MPC8540 Datasheet(PDF) 600 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 600 Page - Freescale Semiconductor, Inc

Back Button MPC8540 Datasheet HTML 596Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 597Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 598Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 599Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 600Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 601Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 602Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 603Page - Freescale Semiconductor, Inc MPC8540 Datasheet HTML 604Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 600 / 1302 page
background image
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
13-96
Freescale Semiconductor
Local Bus Controller
The logical address is partitioned as shown in Table 13-40.
The following parameters can be extracted:
•
COLS = 100, 11 column lines
•
ROWS = 100, 13 row lines
During the address phase, the SDRAM address port is set as in Table 13-41.
Because the internal bank selects are multiplexed over LA[15:16], LSDMR[BSMA] must be set
to 011.
Table 13-42 shows the address port settings during a READ/WRITE command.
Table 13-43 shows the register configuration. PSRT and MPTPR are not shown, but they should
be programmed according to the specific device’s refresh requirements.
Table 13-40. Logical Address Partitioning
A[0:3]
A[4:16]
A[17:18]
A[19:29]
A[30:31]
msb of start address
Row
Bank select
Column
lsb
Table 13-41. SDRAM Device Address Port During Address Phase
LA[0:13]
LA[15:16]
LA[17:29]
LA[30:31]
—
Internal bank select (A[17:18])
Row (A[4:16])
No-connect
Table 13-42. SDRAM Device Address Port During READ/WRITE Command
LA[0:14]
LA[15:16]
LA[17]
LA[18]
LA[19:29]
LA[30:31]
msb of start address
Internal bank select
Don’t care
AP
Column
No-connect
Table 13-43. Register Settings for 512-Mbyte SDRAMs
Register
Field
Value
BRn
BA
Base address
XBA
ext. Base address
PS
11 = 32-bit port size
MS
011 = SDRAM-local bus
V1
ORn
AM
11_1110_0000_0000_0000_0
XAM
11
BPD
01
COLS
100
ROWS
100



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com