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MPC8540 Datasheet(PDF) 598 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 598 Page - Freescale Semiconductor, Inc |
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598 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 13-94 Freescale Semiconductor Local Bus Controller Consider the following SDRAM organization: • The 32-bit port size is organized as 8 x 8 x 32 Mbit. • Each device has four internal banks, 13 row address lines, and 10 column address lines. The logical address is partitioned as shown in Table 13-36. The following parameters are extracted: • COLS = 011, 10 column lines • ROWS = 100, 13 row lines During the address phase, the SDRAM address port is set as shown in Table 13-37. Because the internal bank selects are multiplexed over LA[15:16], LSDMR[BSMA] must be set to 011. Table 13-38 shows the address port configuration during a READ/WRITE command. Table 13-39 shows the register configuration for this example. PSRT and MPTPR are not shown but should be programmed according to the device’s specific refresh requirements. LAD18 A11 LAD17 A12 LAD16 BA0 (if LSDMR[BSMA] = 011) LAD15 BA1 (if LSDMR[BSMA] = 011) Table 13-36. Logical Address Bus Partitioning A[0:4] A[5:17] A[18:19] A[20:29] A[30:31] msb of start address Row Bank select Column lsb Table 13-37. SDRAM Device Address Port during Address Phase LA[0:14] LA[15:16] LA[17:29] LA[30:31] — Internal bank select A[18:19] Row A[5:17] No-connect Table 13-38. SDRAM Device Address Port during READ/WRITE Command LA[0:14] LA[15:16] LA[17:18] LA[19] LA[20:29] LA[30:31] msb of start address Internal bank select Don’t care AP Column No-connect Table 13-35. LADn Signal Connections to 128-Mbyte SDRAM (continued) LAD (latch address) SDRAM Address Pin |
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