MPC8540 datasheet(595/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-91

All the chip selects share the same local bus SDRAM mode register (LSDMR) for initialization

along with the local bus-assigned SDRAM refresh timer register (LSRT) and the memory refresh

timer prescaler register (MPTPR) for refresh.

For refresh, the memory controller supplies auto refresh to SDRAM according to the time interval

specified in LSRT and MPTPR as follows:

This represents the time period required between refreshes. When the refresh timer expires, the

memory controller issues a CBR to each chip select. Each CBR is separated by one clock. A

refresh timing diagram for multiple chip selects is shown in Figure 13-51 in Section 13.4.3.11.1,

“SDRAM Refresh Timing.”

During a memory transaction dispatched to the local bus, the memory controller compares the

memory address with the address information of each chip select (programmed with BRn and

ORn). If the comparison matches a chip select that is controlled by SDRAM, the memory

controller requests service to the local bus SDRAM machine, depending on the information in

BRn. Although multiple chip selects may be programmed for SDRAM, only one chip select is

active at any given time; thus, multiple chip selects can share the same SDRAM machine.

13.5.4.2

Maximum Amount of SDRAM Supported

Table 13-34 summarizes information based on SDRAM data sheets supplied by Micron.

The data port size is programmable, but the following examples use all 32 bits of the local bus.

The 32-bit port size requires four SDRAM devices (with 8-bit I/O ports) connected in parallel to

a single chip select. If 128-Mbit devices are used, one chip select provides 128-Mbit/device x 4

devices = 64 Mbytes. If 4 chip selects are programmed for SDRAM use, the result is 64 Mbytes x

4 = 256 Mbyte. If 256-Mbit SDRAM devices are used, the total available memory is 512 Mbyte.

Consequently 512-Mbit devices allow for 1 Gbyte.

Although there is no technical difficulty in supporting multiple chip select configurations, in

practice, the user may want to maximize the amount of SDRAM assigned to each chip select to

minimize cost.

Table 13-34. Micron SDRAM Devices

SDRAM

Device

64 Mbit

128 Mbit

256 Mbit

512 Mbit

I/O Port

x16

x32

x16

x32

x16

x32

x16

x32

Bank

Row

TBD

Column

TBD

Refresh Period

LSRTx MPTPR PTP

[]

()

System Frequency

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