MPC8540 datasheet(603/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-99

13.5.4.3.8 SDRAM Timing

To allow for very high speeds on the memory bus, the capacitive loading on the local bus must be

taken into consideration as shown in Table 13-44.

Note: Capacitance values compiled from worst case numbers from various data sheets from Samsung and Micron

To implement a system using the hierarchy described earlier for two synchronous memory banks,

one address latch and one buffer loading the multiplexed address/data bus sees a loading of four

loads of about 6.5 pF maximum. 30 pF can be used as a nominal load.

Note: AC characteristics compiled from worst-case numbers from various data sheets from Samsung and Micron

Setup and Hold Timing Calculations:

Address TOF (time of flight): board layout delay

Data TOF (time of flight): board layout delay

Table 13-44. SDRAM Capacitance

Min

Max

Unit

CLK

2.0

4.0

RAS, CAS, WE, CS, CKE, DQM

2.0

5.0

Address

2.0

5.0

DQ0–DQ31

3.5

6.5

Table 13-45. SDRAM AC Characteristics

Parameter

Device Speed

Unit

166 MHz

133 MHz

Min

Max

Min

Max

CLK cycle time

CAS latency = 3

1000

7.5

1000

CAS latency = 2

—

7.5

CLK to valid output delay

CAS latency = 3

—

5.4

CAS latency = 2

—

5.4

Output data hold time

CAS latency = 3

2.5

—

CAS latency = 2

—

Input setup time

1.5

—

Input hold time

—

CLK to output in Hi-Z

CAS latency = 3

—

5.4

—

CAS latency = 2

—

5.4

—

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