MPC8540 datasheet(621/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-117

Synchronous Burst Read

Figure 13-90 shows a synchronous burst read access. The DSI samples HA, HDST, HCID,

HWBE, HRDE, and HBRST on the first HCLKIN rising edge on which HCS is asserted. If

HCID[0:3] match the CHIPID value, the DSI is accessed.

Figure 13-90. Synchronous Burst Read from MSC8102 DSI

HRDE and HBRST are asserted and HWBE are negated. When the DCR[8]:RPE bit (see the

MSC8102 documentation) is set, a burst read access initiates data prefetching from consecutive

addresses in the internal memory space. Assertion of HTA indicates that data is valid for the

current beat of the access and the host must proceed to the next beat of this access. Because HTA

is connected to the LUPWAIT signal of the UPM, all local bus signals are frozen until HTA goes

to 0 and then the UPM continues in its pattern. When the host reaches the last beat of the access,

it must terminate the burst access. The HTA is asserted earlier when the data for this access is

already prefetched to the read buffer. Typically, after the first beat of the burst access, HTA remains

asserted until the end of the access. After the last beat of the access, HTA is driven to 1 and stops

being driven in the next rising edge of HCLKIN. The host can start its next access to the same

MSC8102 immediately in the next HCLKIN rising edge without negating HCS between accesses.

If the next access is not to the same MSC8102, to prevent contention on HTA, the host must wait

to access the next device until the previous DSI stops driving the HTA signal. The easiest way to

achieve this is insert idle cycles at the end of the UPM pattern to guarantee that HTA is inactive.

HCLKIN

D(A+n)

D(A+2)

D(A+1)

D(A+2)

HCS

HCID[0:3]

HA[11:29]

HDST[0:1]

HD[0:63]

HWBE[0:7]

HRDE

HBRST

HTA

Legend:

Timing conventions:

Valid value that can be 1 or 0

Don’t care

Three-state output signal that is not driven by the DSI

n = 3 in 64-bit data bus interface

n = 7 in 32-bit data bus interface

D(A)

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