MPC8540 datasheet(624/1302 Pages) FREESCALE

Part #	MPC8540

Description	MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual

PDF	1302 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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624 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-120

Freescale Semiconductor

Local Bus Controller

In any case, the host port requires a HR/W signal. This can be generated by using another LGPL

signal and allows to adopt the timing virtually without restrictions. Alternatively the designer can

invert LBCTL to generate this signal. It is the responsibility of the UPM pattern designer to plan

for the additional delay of that inverter in the UPM pattern to satisfy AC timings at the DSP host

port.

Figure 13-91. Interface to Texas Instruments EHPI in Non-Multiplexed Mode

The DSP does not necessarily have deterministic access times. HRDY indicates whether the EHPI

is ready for an access. If the signal is low, wait states must be inserted in the cycle. The LUPWAIT

function of the UPM provides this mechanism. MxMR[UWPL] must be set to connect to this

active-low signal.

HD[15:0]

HA[19:4]

Latch

HCNTL0

HA[3:0]

HR/W

HCS

HBE[1:0]

HRDY

HINT

HDS1/HDS2

LAD[0:31]

LALE

LA[27:30]

LGPLy or inverted LBCTL

LCSn

LBS[1:0]

LUPWAIT

INTn

LGPLn

Local Bus Interface

LAD[16:31]

RST_MODE

HMODE

EHPI

MPC8540

MPC8540 Datasheet(PDF) 624 Page - Freescale Semiconductor, Inc