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MPC8540 Datasheet(PDF) 625 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 625 Page - Freescale Semiconductor, Inc |
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625 / 1302 page ![]() Initialization/Application Information MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 13-121 Figure 13-92 shows read timing required by the EHPI in non-multiplexed mode. Figure 13-92. EHPI Non-Multiplexed Read Timings Figure 13-93 shows write timing required by the EHPI in non-multiplexed mode. Figure 13-93. EHPI Non-Multiplexed Write Timings 13.5.6.3.1 Expansion to Multiple DSPs The connection shown above can be adapted easily to interface to multiple DSPs instead of only one. Each DSP host port needs to receive its own chip select and interrupt signals, and HRDY must be connected differently, depending on which DSP is used. All other signals can be connected to all host ports in parallel. HCS HDS HR/W HA[18:0] HD[15:0] HRDY† Data Valid Address † While HCS is not selected, HRDY is in Hi-Z state. HCS HDS HR/W HA[18:0] HD[15:0] HRDY† Valid Address Data Valid Data Valid Valid Address † While HCS is not selected, HRDY is in Hi-Z state. |
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