MPC8540 datasheet(622/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-118

Freescale Semiconductor

Local Bus Controller

13.5.6.2.3 Broadcast Accesses

Using HBCS, a host can share one chip-select signal between multiple MSC8102 devices for

broadcasting write accesses. In broadcast mode, the DSI does not drive its HTA signal to prevent

contention between multiple devices driving different values to the same signal. Also, the DSI

does not decode HCID[0:3].

Note that broadcasting is allowed only for write accesses.

The DSI sets the DSI error register (DER) OVF bit if there is an overflow during broadcast

accesses. This bit can be cleared by writing a value of 1 to it.

NOTE

To avoid overflow when accessing DSI registers during broadcast

accesses, wait at least 10 host clock cycles in synchronous mode or 8

internal clock cycles in asynchronous mode between each DSI register

access.

To avoid data corruption, if DER[0]:OVF is set, no broadcast access is written until the bit is reset.

Therefore, after the last broadcast access, and before any regular write access, DER[0]:OVF must

first be read and reset if it is set.

NOTE

In asynchronous mode, write data from a previous access (even a

normal write access) may be lost due to overflow during broadcast

accesses. To prevent such a loss, ensure that previous access data has

propagated to the FIFO or DSI registers, depending on the type of

previous access. This can be achieved by performing a read access

prior to the first broadcast access.

In broadcast accesses, the host must comply with the following rules:

•

In asynchronous mode, HWBS[0:3]/HDBS[0:3] assertion time should be at least the

minimum, which is defined in the AC characteristics section of the MSC8102 Technical

Data sheet.

•

In synchronous mode single access, the host must wait 1 cycle before terminating the

access. Access signals must be in the same valid state during two positive edges of the host

clock cycles. Access duration is two clock cycles (the DSI may translate accesses lasting

longer than two clock cycles as two or more back-to-back accesses).

•

In synchronous mode burst accesses, broadcast accesses are not allowed.

13.5.6.3

Interfacing to EHPI from Texas Instruments TMS320Cxxxx DSPs

The enhanced host port interface (EHPI) on DSPs from Texas Instruments provides a 16-bit-wide

parallel port through which a host processor can directly access the memory of the DSP. The host

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