MPC8540 datasheet(1198/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-58

Freescale Semiconductor

10/100 Fast Ethernet Controller

for the purposes of FEC. The RFC 3309 algorithm uses the following polynomial to calculate the

CRC value: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+x0 or 0x04c11db7.

Given a destination MAC address of DA=01000CCCCCCC, the algorithm results in a CRC

remainder value of 0xA29F4BBC.

Bit-reversing the low-order byte of the CRC value (0xBC) yields BR_CRC = 0x3D = 0b00111101

The high-order 3-bits of the new BR_CRC value are used to select which 32-bit register (of the 8)

to use. This example maps the DA to register 1.

High-order 3 bits of BR_CRC: HO_CRC = 0b001 = 1

The low-order 5 bits are used to select which bit to set in the given register (with a value of 0

setting 0x8000_0000 and 31 setting 0x0000_0001). Therefore, the example DA maps to bit 29 of

Low-order 5 bits of BR_CRC: LO_CRC = 0b11101 = 29

Therefore, GADDR1 is ORed with the value 0x0000_0004.

Additional calculated examples follow:

Example 1:

•

Destination MAC address: DA = 01005E000128

•

CRC remainder value: CRC = 0x821D6CD3

•

Bit-reversed least-significant byte of CRC value: BR_CRC = 0xCB = 0b11001011

•

High-order 3 bits of BR_CRC: HO_CRC = 0b110 = 6

•

Low-order 5 bits of BR_CRC: LO_CRC = 0b01011 = 11

•

GADDR6 = 0x0010_0000

Example 2:

•

Destination MAC address: DA = 0004F0604F10

•

CRC remainder value: CRC = 0x1F5A66B5

•

Bit-reversed least-significant byte of CRC value: BR_CRC = 0xAD = 0b10101101

•

High-order 3 bits of BR_CRC: HO_CRC = 0b101 = 5

•

Low-order 5 bits of BR_CRC: LO_CRC = 0b01101 = 13

•

GADDR5 = 0x0004_0000

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