MPC8540 datasheet(1199/1302 Pages) FREESCALE

1199 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-59

21.6.2.6 Flow Control

Because collisions cannot occur in full-duplex mode, the FEC can operate at the maximum rate.

When the rate becomes too fast for a station’s receiver, the station’s transmitter can send

flow-control frames to reduce the rate. Flow-control instructions are transferred by special frames

of minimum frame size. The length/type fields of these frames have a special value. Table 21-43

shows the flow control frame structure.

When flow-control mode is enabled (MACCFG1[Rx_Flow] is set) and the receiver identifies a

pause-flow control frame, transmission stops for the time specified in the control frame. During

this pause, only a control frame can be sent (TCTRL[TFC_PAUSE] is set). Normal transmission

resumes after the pause timer stops counting. If another pause-control frame is received during the

pause, the period changes to the new value received.

21.6.2.7 Interrupt Handling

The following describes what usually occurs within a FEC interrupt handler:

•

When an interrupt occurs, read IEVENT to determine interrupt sources. IEVENT bits to be

handled in this interrupt handler are normally cleared at this time.

Table 21-43. Flow Control Frame Structure

Size

[Octets

]

Description

Value

Comment

Preamble

SFD

Start frame delimiter

Destination address

01-80C2-00-00-01 Multicast address reserved for use in MAC frames

Source address

Length/type

88-08

Control frame type

MAC opcode

00-01

Pause command

MAC parameter

Pause period measured in slot times, most-significant octet first

with a two time-slot resolution. Note: Because the pause period

has a resolution of two time slots, the value programmed in this

field is rounded up to the nearest even number before being

used, as follows:

MAC Parameter Value

1 or 2

3 or 4

…

Pause Period

None

× slot time

…

Reserved

—

FCS

Frame check sequence (CRC)

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