MPC8540 datasheet(1201/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-61

21.6.2.8 Inter-Packet Gap Time

When a station needs to transmit, it waits until the LAN becomes silent for a specified period

(inter-packet gap). When a station starts sending, it continually checks for collisions on the LAN.

If a collision is detected, the station forces a jam signal (all ones) on its frame and stops

transmitting. Collisions usually occur close to the beginning of a packet. The station then waits a

random time period (back-off) before attempting to send again. When the back-off completes, the

station waits for silence on the LAN and then begins retransmission on the LAN. This process is

called a retry. If the packet is not successfully sent within specified number of retries, an error is

indicated.

The minimum inter-packet gap time for back-to-back transmission is 96 serial clocks. The receiver

receives back-to-back packets with this minimum spacing. In addition, after waiting a required

number of clocks (based on the back-off algorithm), the transmitter waits for carrier sense to be

negated before retransmitting the packet. Retransmission begins 36 serial clocks after carrier sense

is negated for at least 60 serial clocks.

21.6.2.9 Internal and External Loop Back

Setting MACCFG1[Loop_Back] causes MAC transmit outputs to be looped back to the MAC

receive inputs. Clearing it results in normal operation. This bit is cleared by default.

21.6.2.10 Error-Handling Procedure

The Ethernet controller reports frame reception and transmission error conditions using the

channel BDs, the error counters, and the IEVENT register.

Transmission errors are described in Table 21-46.

Table 21-46. Transmission Errors

Error

Response

Transmitter underrun

The FEC sends 32 bits that ensure a CRC error, terminates buffer transmission, sets

TxBD[UN], closes the buffer, sets IEVENT[XFUN] and IEVENT[TXE]. The controller

resumes transmission after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).

Retransmission attempts

limit expired

The FEC terminates buffer transmission, sets TxBD[RL], closes the buffer, sets

IEVENT[CRL/XDA] and IEVENT[TXE]. Transmission resumes after TSTAT[THLT] is

cleared (and DMACTRL[GTS] is cleared).

Late collision

The FEC terminates buffer transmission, sets TxBD[LC], closes the buffer, sets

IEVENT[LC] and IEVENT[TXE]. The controller resumes transmission after TSTAT[THLT]

is cleared (and DMACTRL[GTS] is cleared).

Memory read error

A system bus error occurred during a DMA transaction. The FEC sets IEVENT[EBERR],

DMA stops sending data to the FIFO which causes an underrun error but IEVENT[XFUN]

is not set. The TSTAT[THLT] is set. Transmits are continued once TSTAT[THLT] is cleared.

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