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MPC8540 Datasheet(PDF) 1200 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1200 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
21-60
Freescale Semiconductor
10/100 Fast Ethernet Controller
•
Process the TxBDs to reuse them if the IEVENT[TXB] or IEVENT[TXE] were set. If the
transmit speed is fast or the interrupt delay is long, more than one transmit buffer may have
been sent by the FEC. Thus, it is important to check more than just one TxBD during the
interrupt handler. One common practice is to process all TxBDs in the interrupt handler
until one is found with R set. See Table 21-44.
•
Obtain data from the RxBD if IEVENT[RXC], IEVENT[RXB], or IEVENT[RXF] is set.
If the receive speed is fast or the interrupt delay is long, the FEC may have received more
than one receive buffer. Thus, it is important to check more than just one RxBD during
interrupt handling. Typically, all RxBDs in the interrupt handler are processed until one is
found with bit E set. Because the FEC pre-fetches BDs, the BD table must be big enough
so that there is always another empty BD to pre-fetch. See Table 21-45.
•
Clear any set halt bits in TSTAT and RSTAT registers, or DMACTRL[GTS] and
DMACTRL[GRS].
•
Continue normal execution.
Table 21-44. Non-Error Transmit Interrupts
Interrupt
Description
Action taken by FEC
GTSC
Graceful transmit stop complete: Transmitter is put into a
pause state after completion of the frame currently being
transmitted.
None
TXC
Transmit control: Instead of the next transmit frame, a control
frame was sent.
None
TXB
Transmit buffer: A TxBD, that is not the last one in the frame,
was updated.
Programmable write-with-response TxBD
to memory before setting IEVENT[TXB].
TXF
Transmit frame: A frame was transmitted and the last TxBD of
that frame was updated.
Programmable write-with-response to
memory on the last TxBD before setting
IEVENT[TXF].
Table 21-45. Non-Error Receive Interrupts
Interrupt
Description
Action taken by FEC
GRSC
Graceful receive stop complete: Receiver is put into a pause
state after completion of the frame currently being received.
None
RXC
Receive control: A control frame was received. As soon as
the transmitter finishes sending the current frame, a pause
operation is performed lasting for the duration specified in
the received pause control frame and beginning when the
frame was first received.
None
RXB
Receive buffer: An RxBD, that is not the last one of the
frame, was updated.
Programmable write-with-response RxBD to
memory before setting IEVENT[RXB].
RXF
Receive frame: A frame was received and the last RxBD of
that frame was updated.
Programmable write-with-response to
memory on the last RxBD before setting
IEVENT[RXF].



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