MPC8540 datasheet(1203/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-63

Reception errors are described in Table 21-47.

21.6.3 Buffer Descriptors

The FEC buffer descriptor (BD) is modeled after the MPC8260 Fast Ethernet controller BD for

ease of reuse.

Drawing from the MPC8260 FEC BD programming model, the FEC descriptor base registers

point to the beginning of BD rings.

There is an 8-byte data BD format designed to be similar to the existing MPC8260 BD model.

The FEC is capable of placing extracted data directly into the L2 cache memory. This allows the

processor to quickly access critical frame information as soon as the processor is ready without

having to first fetch the data from main memory. This results in substantial improvement in

throughput and hence reduction in latency.

Data buffers are used in the transmission and reception of Ethernet frames (see Figure 21-44).

Data BDs encapsulate all information necessary for the FEC to transmit or receive an Ethernet

frame. Within each data BD there is a status field, a data length field, and a data pointer. The BD

completely describes an Ethernet packet by centralizing status information for the data packet in

the status field of the BD and by containing a data BD pointer to the location of the data buffer.

Software is responsible for setting up the BDs in memory. Because of prefetching, at least two

buffer descriptors per ring are required. This applies to both the transmit and the receive descriptor

rings. Software also must have the data pointer pointing to memory. An ownership bit in the status

field defines the current state of the buffer (pointed to by the data pointer). Other status field bits

Table 21-47. Reception Errors

Error

Description

Overrun error The FEC maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer overrun occurs, the

controller sets RxBD[OV], sets RxBD[L], closes the buffer, and sets IEVENT[RXF], The receiver then

enters hunt mode (seeking start of a new frame).

Busy error

A frame is received and discarded due to a lack of buffers. The FEC sets IEVENT[BSY]. In addition,

RSTAT[RHLT] is set. The halted queue resumes reception once the user clears RSTAT[RHLT].

Non-octet

error

(dribbling

bits)

The Ethernet controller handles a nibble of dribbling bits if the receive frame terminates as non-octet

aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC error, the frame

non-octet aligned (RxBD[NO]) error is reported, IEVENT[RXF] is set, and the alignment error counter

increments. The FEC relies on the statistics collector block to increment the receive alignment error

counter (RALN). If there is no CRC error, no error is reported.

CRC error

If a CRC error occurs, the FEC sets RxBD[CR], closes the buffer, and sets IEVENT[RXF]. This FEC relies

on the statistics collector block to record the event. After receiving a frame with a CRC error, the receiver

then enters hunt mode.

Memory

Read Error

A system bus error occurred during a DMA transaction. The FEC sets IEVENT[EBERR] and discards the

frame. Also, RSTAT[RHLT] is set. The halted queue resumes reception once RSTAT[RHLT] is cleared.

Babbling

Receive Error

A frame is received that exceeds the MAC’s maximum frame length. The FEC sets IEVENT[BABR] and

continues.

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