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MPC8540 Datasheet(PDF) 1206 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1206 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
21-66
Freescale Semiconductor
10/100 Fast Ethernet Controller
Offset + 0
4
L
Last in frame. Written by user.
0 The buffer is not the last in the transmit frame.
1 The buffer is the last in the transmit frame.
Offset + 0
5
TC
Tx CRC. Written by user. (Valid only while it is set in first BD and TxBD[PAD/CRC]
is cleared and MACCFG2[PAD/CRC] is cleared and MACCFG2[CRC EN] is
cleared.) If MACCFG2[PAD/CRC] is set or MACCFG2[CRC EN] is set, this bit is
ignored.
0 End transmission immediately after the last data byte with no hardware
generated CRC appended, unless TxBD[PAD/CRC] is set.
1 Transmit the CRC sequence after the last data byte.
Offset + 0
6
DEF
Defer indication. Hardware updates this bit if an excessive defer condition occurs.
0 This frame was not deferred.
1
If HAFDUP[EXCESS_DEFER]=1, this frame did not have a collision before it
was sent but it was sent late because of deferring. If
HAFDUP[EXCESS_DEFER]=0, this frame was aborted and not sent.
Offset + 0
7
TO1
Transmit software ownership. This read/write bit may be utilized by software, as
necessary. Its state does not affect the hardware nor is it affected by the hardware.
Offset + 0
8
HFE/LC
Huge frame enable (written by user)/Late collision (written by the FEC)
Huge frame enable. Written by user. Valid only while it is set in first BD and the
MACCFG2[Huge Frame] is cleared. If MACCFG2[Huge Frame] is set, this bit is
ignored.
0 Truncate transmit frame if its length is greater than the MAC’s Maximum Frame
Length register.
1 Do not truncate the transmit frame.
Late collision. Written by the FEC.
0 No late collision.
1 A collision occurred after 64 bytes are sent. The FEC terminates the
transmission and updates LC.
Offset + 0
9
RL
Retransmission Limit. Written by the FEC.
0 Transmission before maximum retry limit is hit.
1 The transmitter failed (maximum retry limit + 1) attempts to successfully send
a message due to repeated collisions. The FEC terminates the transmission
and updates RL.
Offset + 0
10–13
RC
Retry Count. Written by the FEC.
0 The frame is sent correctly the first time or if RL is set then the retry limit has
been reached
x One or more attempts where needed to send the transmit frame. If this field is
15, then 15 or more retries were needed. The Ethernet controller updates RC
after sending the buffer.
Offset + 0
14
UN
Underrun. Written by the FEC.
0 No underrun encountered (data was retrieved from external memory in time to
send a complete frame).
1 The Ethernet controller encountered a transmitter underrun condition while
sending the associated buffer. The FEC terminates the transmission and
updates UN.
Table 21-48. Transmit Data Buffer Descriptor (TxBD) Field
Descriptions (continued)
Offset
Bits
Name
Description



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