MPC8540 datasheet(1208/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

21-68

Freescale Semiconductor

10/100 Fast Ethernet Controller

Offset + 0

Interrupt. Written by user.

0 No interrupt is generated after this buffer is serviced.

1 IEVENT[RXB] or IEVENT[RXF] are set after this buffer is serviced. This bit can cause

an interrupt if enabled (IMASK[RXBEN] or IMASK[RXFEN]). If the user wants to be

interrupted only if RXF occurs, then the user must disable RXB (IMASK[RXBEN] is

cleared) and enable RXF (IMASK[RXFEN] is set).

Offset + 0

Last in frame. Written by the FEC.

0 The buffer is not the last in a frame.

1 The buffer is the last in a frame.

Offset + 0

First in frame. Written by the FEC.

0 The buffer is not the first in a frame.

1 The buffer is the first in a frame.

Offset + 0

—

Reserved

Offset + 0

Miss. Written by the FEC. (This bit is valid only if L is set and the FEC is in promiscuous

mode.)

This bit is set by the FEC for frames that were accepted in promiscuous mode, but were

flagged as a ‘miss’ by the internal address recognition; thus, while in promiscuous mode,

the user can use bit M to quickly determine whether the frame was destined to this

station.

0 The frame was received because of an address recognition hit.

1 The frame was received because of promiscuous mode.

Offset + 0

Broadcast. Written by the FEC. (Only valid if L is set.) Is set if the DA is broadcast

(FF-FF-FF-FF-FF-FF).

Offset + 0

Multicast. Written by the FEC. (Only valid if L is set.) Is set if the DA is multicast and not

BC.

Offset + 0

Rx frame length violation. Written by the FEC (only valid if L is set).

A frame length greater than maximum frame length was recognized while

MACCFG2[Huge Frame] was set. Note, if MACCFG2[Huge Frame] is cleared, the frame

is truncated to the value programmed in the maximum frame length register.

Offset + 0

Rx non–octet-aligned frame. Written by the FEC (only valid if L is set).

A frame that contained a number of bits not divisible by eight was received.

Offset + 0

Short frame. Written by the FEC (only valid if L is set).

A frame length that was less than the minimum length defined for this channel (MINFLR)

was recognized, provided RCTRL[RSF] is set.

Offset + 0

Rx CRC error. Written by the FEC (only valid if L is set).

This frame contains a CRC error and is an integral number of octets in length.This bit is

also set if a receive code group error is detected.

Offset + 0

Overrun. Written by the FEC (only valid if L is set).

A receive FIFO overrun occurred during frame reception. If this bit is set, the other status

bits, M, LG, NO, SH, CR, and CL lose their normal meaning and are zero.

Offset + 0

Truncation. Written by the FEC (only valid if L is set).

Is set if the receive frame is truncated. This can happen if a frame length greater than

maximum frame length was received and the MACCFG2[Huge Frame] is cleared. If this

bit is set, the frame must be discarded and the other error bits must be ignored as they

may be incorrect.

Table 21-49. Receive Buffer Descriptor Field Descriptions (continued)

Offset

Bits

Name

Description

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