MPC8540 datasheet(1211/1302 Pages) FREESCALE

1211 / 1302 page

Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

21-71

Table 21-51 describes the register initializations required to reconfigure the PHY to MII mode

following intial auto-negotiation.

Table 21-51. MII Mode Register Initialization Steps

Set Soft_Reset,

MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]

Clear Soft_Reset,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize MACCFG2, for MII, half duplex operation.

Set I/F Mode bit to nibble mode,

MACCFG2[0000_0000_0000_0000_0111_0001_0000_0100]

(This example has Full Duplex = 0, Preamble count = 7, PAD/CRC append = 1)

Initialize MAC Station Address,

MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]

Set station address to 02_60_8C_87_65_43, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Initialize MAC Station Address,

MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]

Set station address to 02_60_8C_87_65_43, for example.

(Note that PHY configuration register addresses are not necessarily consistent in all PHYs.)

Check auto-negotiation attributes in the PHY as necessary.

Clear IEVENT register,

IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IMASK, (Optional)

IMASK[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize IADDRn, (Optional)

IADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize GADDRn, (Optional)

GADDRn[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize RCTRL, (Optional)

RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize DMACTRL, (Optional)

DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

Initialize (Empty) Transmit Descriptor ring and fill buffers with Data.

Initialize TBASE,

TBASE[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]

Initialize (Empty) Receive Descriptor ring and fill with empty buffers.

Initialize RBASE,

RBASE[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]

Enable Rx and Tx,

MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]

MPC8540 Datasheet(PDF) 1211 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1211 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL