MPC8540 datasheet(1215/1302 Pages) FREESCALE

1215 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-3

4.4.4.1, 4-23

Replace the existing Figure 4-6 with the following figure (Note the addition

of the CCB clock dividers prior to the DDR DLL and the LBC DLL):

4.4.4.4, 4-25

In Figure 4-8, replace the sentence:

“Watchdog timer events based on one of the 64 TB bits selected by

TCR[WP] concatenated with the EIS-defined TCR[WPEXT]

(WP||WPEXT).”

with the following sentence:

“Watchdog timer events based on one of the 64 TB bits selected by

concatenating TCR[WPEXT] with the EIS-defined TCR[WP]

(WPEXT||WP).”

4.4.4.4, 4-25

In Figure 4-8, replace the sentence:

“Fixed-interval timer events based on one of the 64 TB bits selected by

TCR[FP] concatenated with the EIS-defined TCR[FPEXT] (FP||FPEXT).”

with the following sentence:

“Fixed-interval timer events based on one of the 64 TB bits selected by

concatenating TCR[FPEXT] with the EIS-defined TCR[FP] (FPEXT||FP).”

LCLK2

Core PLL

Device PLL

DLL

MSYNC_IN

LSYNC_IN

LSYNC_OUT

LCLK0

LCLK1

MSYNC_OUT

MCK[0:5]

core_clk

e500 Core

CCB_clk to Rest of the Device

SYSCLK/

PCI_CLK

CCB_clk

cfg_sys_pll[0:3]

cfg_core_pll[0:1]

MPC8540

DDR

Controller

LBC

MPC8540 Datasheet(PDF) 1215 Page - Freescale Semiconductor, Inc

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