MPC8540 datasheet(1218/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-6

Freescale Semiconductor

Revision History

6.11.3, 6-30

In Table 6-20, describe bits 34–38 as ‘Reserved’ as is properly expressed in

Figure 6-35. Disregard descriptions associated with bits 34, 35, or 36 in

Table 6-20.

6.12.2, 6-32

In Figure 6-38 and Table 6-22, describe bits 59 and 60 as “Reserved”.

6.12.5.3, 6-37

In Table 6-28, describe bits 52–56 as “Reserved for

implementation-specific use”.

6.13.3, 6-45

Remove all references to IAC3 and IAC4 from this section.

7.3.1.1, 7-8

In Table 7-2, change the description for bit 1 from “Accesses to

memory-mapped SRAM are unaffected...” to “Data in memory-mapped

SRAM regions is unaffected...”

7.3.1.1, 7-8 and 7-9

In Figure 7-7 and Table 7-2, show bit 11 to be reserved.

7.3.1.5.2, 7-16 and 7-17

In Table 7-12, change the bit descriptions for bits 27 and 31 of the

L2ERRDET register as follows:

Bit 27, TPARERR: Add the following text: “Note that if an L2 cache tag

parity error occurs on an attempt to write a new line, the L2 cache must be

flash invalidated. L2 functionality is not guaranteed if flash invalidation is

not performed after a tag parity error.”

Bit 31, L2CFGERR: Add the following text to the 1st line of description,

“Reports inconsistencies between the L2SIZ, L2BLKSZ, and L2SRAM

settings of the L2 control register (L2CTL).”

7.7.4, 7-25

Add the following note after the second paragraph:

NOTE

There is a scenario in which a lock clear operation appears to fail to

clear a lock in the L2 cache. This occurs only when the attempt to set

the lock results in a bus error (for example, PCI returns an error

condition).

Assume the following scenario:

1. The e500 attempts to set a lock in the L2 cache (by executing a

dcbtls or icbtls instruction with CT = 1). The line is not already

present in the cache, so it must be read from external memory. This

read encounters an error which, depending on the chip configuration,

will be reported to the core (probably as an interrupt).

2. At (or near) the same time, a cache external write to the same cache

line is being mastered by the ECM.

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