MPC8540 datasheet(1222/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-10

Freescale Semiconductor

Revision History

9.4.1.1, 9-10

In Table 9-6, change the CSn_BNDS[EAn] field description to read:

“Ending address for chip select (bank) n. This value is compared against the

8 msbs of the address.”

9.4.1.4, 9-13

In Table 9-9, replace all instances of |CASLAT| with

9.4.1.5, 9-14

In Table 9-10, change the setting of the MBEE bit in the

DDR_SDRAM_CFG[ECC_EN] description to read as follows:

“ECC enable. Note that uncorrectable read errors may cause the assertion

of core_fault_in, which causes the core to generate a machine check

interrupt unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero

and this error occurs, ERR_DISABLE[MBED] must be zero and

ERR_INT_EN[MBEE] and ECC_EN must be one to ensure an interrupt is

generated. See Section 6.10.2, “Hardware Implementation-Dependent

No ECC errors are reported. No ECC interrupts are generated.

ECC is enabled.”

9.4.1.7, 9-16

In Table 9-12, add the following last sentence to the

DDR_SDRAM_INTERVAL[REFINT] field description:

“Note that REFINT must be set to a non-zero value in order for the DDR to

enter sleep mode. See Section 18.5.1.5.3, “Sleep Mode,” for additional

details.”

9.4.1.15, 9-21

Change the setting of MBEE bit in the ERR_DISABLE[MBED]

description to read as follows:

Multiple-bit ECC error disable

Multiple-bit ECC errors are detected if

DDR_SDRAM_CFG[ECC_EN] is set. They are reported if

ERR_INT_EN[MBEE] is set. Note that uncorrectable read errors

cause the assertion of core_fault_in, which causes the core to generate

a machine check interrupt, unless it is disabled (by clearing

HID1[RFXE]). If RFXE is zero and this error occurs, MBED must be

zero and ERR_INT_EN[MBEE] and ECC_EN must be one to ensure

that an interrupt is generated.

Multiple-bit ECC errors are not detected or reported.

9.4.1.16, 9-21

Change the setting of the MBEE bit in the ERR_INT_EN[MBEE]

description to read as follows:

“Multiple-bit ECC error interrupt enable. Note that uncorrectable read

errors may cause the assertion of core_fault_in, which causes the core to

CASLAT

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