MPC8540 datasheet(1220/1302 Pages) FREESCALE

1220 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-8

Freescale Semiconductor

Revision History

7.9.1.2 Memory-Mapped SRAM Initialization

After power-on reset, the contents of the data and ECC arrays and are

random, so all SRAM data must be initialized before it is read. If the cache

is initialized by the core or any other device that uses sub-cacheline

transactions, ECC error checking should be disabled during the

initialization process to avoid false ECC errors generated during the

read-modify-write process used for sub-cacheline writes to the SRAM

array. This is done by setting the multi- and single-bit ECC error disable bits

of the L2 error disable register (L2ERRDIS[MBECCDIS, SBECCDIS]).

See Section 7.3.1.9.2, “Error Control and Capture Registers.” If the array is

initialized by a DMA engine using cache-line writes, then ECC checking

can remain enabled during the initialization process.

Also, add new Section 7.10.2, “Managing Errors,” with subsections Section

7.10.2.1, “ECC Errors,” and Section 7.10.2.2, “Tag Parity Errors.”

7.10.2.1 ECC Errors

An individual soft error that causes a single- or mulit-bit ECC error can be

cleared from the L2 array simply by executing a dcbf instruction for the

address captured in the L2ERRADDR register. This will invalidate the line

in the L2 cache. When the load that caused the ECC error is performed

again, the data will be re-allocated into the L2 with ECC bits set properly

again.

If the threshold for single bit errors set in the L2ERRCTL register is

exceeded, then the L2 cache should be flash invalidated to clear out all

single-bit errors.

Note that no data is lost by executing dcbf instructions or flash invalidate

operations because the L2 cache is write-through and contains no modified

data.

7.10.2.2 Tag Parity Errors

A tag parity error must be fixed by flash invalidating the L2 cache. Note that

executing a dcbf instruction for the address that caused the error to be

reported is not sufficient because a tag parity error is seen as an L2 miss and

does not cause invalidation of the bad tag. Proper L2 operation cannot be

MPC8540 Datasheet(PDF) 1220 Page - Freescale Semiconductor, Inc