MPC8540 datasheet(1221/1302 Pages) FREESCALE

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Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-9

guaranteed if an L2 tag parity error is not repaired by a flash invalidation of

the entire array.

9.3.2.1, 9-6

In Table 9-3, change the Timing description for the MA[0:14] signals to

read:

“Assertion/Negation—The address is always driven when the memory

controller is active. It is valid when a transaction is driven to DRAM (when

MCSn is negated).

High-impedance—When the memory controller is idle.”

9.3.2.1, 9-6

In Table 9-3, change the Timing description for the MCAS signal to read:

“Assertion/Negation—Assertion and negation timing is directed by the

values described in Section 9.4.1.3, “DDR SDRAM Timing

Configuration 1 (TIMING_CFG_1).”

High-impedance—MCAS is always driven unless the memory controller is

idle.”

9.3.2.1, 9-7

In Table 9-3, change the Timing description for the MRAS signal to read:

“Assertion/Negation—Timing is directed by the values described in Section

9.4.1.3, “DDR SDRAM Timing Configuration 1 (TIMING_CFG_1).”

High-impedance—MRAS is always driven unless the memory controller is

idle.”

9.3.2.1, 9-7

In Table 9-3, change the Timing description for the MWE signal to read:

“Assertion/Negation—Similar timing as MRAS and MCAS. Used for write

commands.

High-impedance—MWE is always driven unless the memory controller is

idle.”

9.3.2.2, 9-8

In Table 9-4, correct the “MCKE” signal name to read “MCKE[0:1]”.

Also, change the first full sentence of the MCKE[0:1] signal description to

read:

“Two identical output signals (each hereafter referred to simply as MCKE)

used as the clock enable to one or more SDRAMs.”

9.3.2.2, 9-8

In Table 9-4, change the Timing description for the MCKE[0:1] signal to

read:

“Assertion/Negation—Similar timing to MAn.

High-impedance—Always driven.”

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