MPC8540 datasheet(1225/1302 Pages) FREESCALE

1225 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-13

9.5.8.1, 9-40

In Figure 9-33, remove the annotation of “0 or 3” in clock 12.

9.5.8.2, 9-41

After the second paragraph, add the following paragraph:

“All open pages are precharged before self refresh mode is entered.”

Also, correct the last sentence of the fifth paragraph to read:

“This mode is controlled with DDR_SDRAM_CFG[DYN_PWR].”

9.5.9, 9-43

Replace the third and fourth sentences of this section with the following:

“If ECC is enabled for a sub-doubleword write transaction, a full

read-modify-write is performed to properly update ECC bits. If ECC is

disabled then no read-modify-write is required for sub-doubleword writes,

and the data masks (MDM[0:8]) are used to prevent writing unwanted data

to SDRAM.”

9.5.11, 9-44

Add the following sentences before the second-to-last sentence of the

second paragraph:

“This read-modify-write operation is performed as an atomic transaction in

the DDR controller. The write command is then issued 3-5 memory clocks

after the completion of the read, depending on various system parameters.”

9.5.12, 9-46

In the last paragraph, delete the three sentences that start and end with, “For

all memory select errors...” and “...to show the transaction is not real.”

9.6.1, 9-48

In the second sentence, replace “after the DLL has locked” with the

following:

“after the memory clocks are stable (that is, the DLL has locked or

initialization is complete of all clock related configuration registers).”

Replace the last sentence of the first paragraph with the following:

“After MEM_EN has been set, the DDR memory controller automatically

performs the JEDEC-compliant initialization sequence to initialize

memories according to the information in the SDMODE and ESDMODE

fields of the DDR_SDRAM_MODE register. The initialization sequence is

as follows:”

After the numbered list, add the following sentence:

“Note that the BA0 and BA1 bits are automatically driven appropriately

during the MODE REGISTER SET commands.” Then the final sentence

should be changed to, “After this automatic initialization is complete the

memory array is ready for access and the memory controller begins

processing memory transactions as they arrive.”

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