MPC8540 datasheet(1229/1302 Pages) FREESCALE

1229 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-17

13.4.4.2, 13-65

Add the following third paragraph:

“Note that the UPM memory region must be cache-inhibited or

write-through (the MMU page must have the I or W bit set) during the time

that the UPM array is being written. If the memory is to be cacheable and/or

copyback, the MMU must be set accordingly after the UPM array is

initialized.”

13.4.7.3, 13-55

In the section title, change “CAS” to “CAS”.

Chapter 14, 21

For consistency, change all instances of “HFE”, “Huge_Frame”, and

“HUGE FRAME” to “Huge Frame”.

14.2, 14-7

In the first bullet item of the TSEC features list, change “820.3x” to

“802.3x.”

14.2, 14-7

Change the fifth element of the second bullet item in the TSEC features list

to read:

“– 10/100 Mbps RMII”

14.5.2, 14-14

In Table 14-3, add the following as the first row under the TSEC1 FIFO

Control and Status Registers section:

14.5.2, 14-15

In Table 14-3, correct the reset value for the OSTBD register to

0x0800_0000.

14.5.2, 14-16

In Table 14-3, correct the MACCFG1 register from having R/W, R access

to R/W access.

14.5.2, 14-16

In Table 14-3, correct the IFSTAT register from having R access to R/W

access.

14.5.2, 14-16

In Table 14-3, change the reset value for the TSEC IFSTAT register to be

0x0000_0000.

14.5.2, 14-18

In Table 14-3, correct the CAR1 and CAR2 registers from having R access

to R/W access.

14.5.2, 14-18

In Table 14-3, remove the incorrect "Cleared on read" footnote designation

from the CAR1 and CAR2 registers.

14.5.2, 14-19

In Table 14-3, correct the ATTR and ATTRELI registers from having R

access to R/W access.

14.5.3.1.1, 14-20

In Table

14-4, correct the IEVENT[RXC] bitfield description to read as follows:

“Receive control interrupt. A control frame was received. If

MACCFG1[Rx_Flow] is set, a pause operation is performed lasting for the

0x2_404C

FIFO_PAUSE_CTRL—FIFO pause control register

R/W

0x0000_0000

14.5.3.2.1/A-19

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