MPC8540 datasheet(1233/1302 Pages) FREESCALE

1233 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-21

14.5.3.6.1, 14-47

Replace Figure 14-34 with the following figure:

14.5.3.6.1, 14-48

In Table 14-32, add the following sentence to the MACCFG1[Rx_EN] field

description:

“If set, prior to clearing this bit, set DMACTRL[GRS] then confirm

subsequent occurrence of the graceful receive stop interrupt

(IEVENT[GRSC] is set).”

14.5.3.6.1, 14-48

In Table 14-32, add the following sentence to the MACCFG1[Tx_EN] field

description:

“If set, prior to clearing this bit, set DMACTRL[GTS] then confirm

subsequent occurrence of the graceful transmit stop interrupt

(IEVENT[GTSC] is set).”

14.5.3.6.6, 14-52

In Table 14-37, clarify the bit description of the Mgmt Clock Select field of

the MIIMCFG register so that instead of concluding with “... divided by

eight.” the third sentence concludes with “... divided first by eight and then

futher divided by the following value:”.

14.5.3.6.12, 14-55

Delete the first sentence and replace Figure 14-45 with the following figure

(exposing the Link Fail status field):

Soft_Reset

00 00 0 0

0 0

Reset

Rx MC

Reset

Tx MC

Reset

Rx Fun

Reset

Tx Fun

Reset

0000_0000_0000_0000

24 25

00 00 0 0

Loop Back

Rx_Flow Tx_Flow

Sync’d Rx EN

Rx_EN

Sync’d Tx EN

Tx_EN

Reset

0000_0000_0000_0000

Offset

TSEC1:0x2_4500; TSEC2:0x2_5500

00000000 0000000000000

Excess

Defer

0000

Link

Fail

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_453C; TSEC2:0x2_553C

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