MPC8540 datasheet(1232/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-20

Freescale Semiconductor

Revision History

pause frame. Next, the MAC clears TFC_PAUSE and resumes transmitting

data frames. Note that if the transmitter is paused due to user assertion of

GTS or reception of a PAUSE frame, the MAC may still transmit a MAC

control PAUSE frame.

No outstanding pause frame transmission request.

Pause frame transmission requested.”

14.5.3.3.6, 14-35

Change the last sentence in the first paragraph to read:

“Although not necessary in most applications, the user can modify this

indicated by IEVENT[GTSC] or TSTAT[THLT].”

14.5.3.3.8, 14-38

In Table 14-22, add the following sentence to the OSTBDLEN field

description:

“This field must be greater than zero in order for a transfer to take place.”

14.5.3.4.2, 14-40

In Table 14-25, change the description for the RSTAT[QHLT] field to read:

“RxBD queue is halted. When IEVENT[BSY] or IEVENT[EBERR] is set

during reception of a packet, RSTAT[QHLT] is also set. In order to begin

receiving packets again, the user must clear RSTAT[QHLT]. This bit is set

whenever the TSEC reads an RxBD with its Empty field cleared or

encounters a system bus error while processing an RX packet. It is a

hardware-initiated stop indication (DMA_CTRL[GRS] being set by the

user does not cause this bit to be set.). The current frame and all other frames

directed to the halted queue are discarded. A write with a value of 1

re-enables the queue for receiving.

RxBD queue is enabled for Ethernet reception. (That is, it is not

halted.)

All Ethernet controller receive activity to RxBD queue is halted.”

14.5.3.4.2, 14-39

Replace Figure 14-27 with the following figure:

789

R0 00 00000

QHLT

000000 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4304; TSEC2:0x2_5304

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