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MPC8540 Datasheet(PDF) 1235 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1235 Page - Freescale Semiconductor, Inc |
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1235 / 1302 page ![]() Changes From Revision 0 to Revision 1 MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor A-23 14.6.2.2, 14-108 Replace the existing procedure list with the following list: “Following is a procedure to gracefully reset and reconfigure the MAC: 1. Set GTS bit in DMACTRL register 2. Poll GTSC bit in IEVENT register until detected as set 3. Clear both Rx_EN and Tx_EN bits in MACCFG1 4. Set GRS bit in DMACTRL register 5. Poll GRSC bit in IEVENT register until detected as set 6. Set Soft_Reset bit in MACCFG1 register 7. Clear Soft_Reset bit in MACCFG1 register 8. Load TBASE with new TxBD pointer 9. Load RBASE with new RxBD pointer 10. Set up other MAC registers (MACCFG1, MAXFRM, and so on) 11. Set WWR, WOP, TOD bits in DMACTRL register 12. Clear THLT bit in TSTAT register and QHLT bit in RSTAT register by writing 1 to these bits 13. Clear GRS/GTS bits in DMACTRL (do not change other bits) 14. Enable Tx_EN/Rx_EN in MACCFG1 register” 14.6.2.2, 14-108 Insert the following step between steps 3 and (formerly) 4: "4. Wait for a period of 9.6 Kbytes worth of data on the interface (~8ms worst case)." 14.6.2.2, 14-109 Correct step 11 of the graceful reset procedure to read: "11. Set WWR and WOP bits in DMACTRL register" 14.6.2.3, 14-109 Replace the second paragraph with the following: "If the user has a frame ready to transmit, a transmit-on-demand function may be emulated while in polling mode by using the graceful-transmit-stop feature. First, clear the IMASK[GTSCEN] bit to mask the graceful-transmit-stop complete interrupt. Next set, then immediately clear the DMACTRL[GTS] bit. Clear the resulting IEVENT[GTSC] bit. Finally, the IMASK[GTSCEN] bit may be set once again." 14.6.2.3, 14-110 Insert the following sentence between the third and (formerly) fourth sentences of the sixth paragraph: "The pause duration is defined by the received pause control frame and begins when the frame was first received." |
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