MPC8540 datasheet(1237/1302 Pages) FREESCALE

1237 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-25

•Low-order 5 bits of BR_CRC: LO_CRC = 0b01011 = 11

•GADDR6 = 0x0010_0000

Example 2:

•Destination MAC address: DA = 0004F0604F10

•CRC remainder value: CRC = 0x1F5A66B5

•Bit-reversed least-significant byte of CRC value: BR_CRC = 0xAD =

0b10101101

•High-order 3 bits of BR_CRC: HO_CRC = 0b101 = 5

•Low-order 5 bits of BR_CRC: LO_CRC = 0b01101 = 13

•GADDR5 = 0x0004_0000

14.6.2.8, 14-116

In Table 14-115, corrected the RXC description to read as follows:

“Receive control: A control frame was received. As soon as the transmitter

finishes sending the current frame, a pause operation is performed lasting

for the duration specified in the received pause control frame and beginning

when the frame was first received.”

14.6.2.11, 14-118

Insert the following paragraph after the first paragraph:

“Programming note: When the TSEC encounters a halt condition

(TSTAT[THLT] is set), it stops processing the frame at the current TxBD.

The TSEC relies on the user to manage the buffer descriptor pointer,

TBPTR, or the buffer descriptor queue before resuming transmissions. Once

the TSEC resumes, it fetches the TxBD pointed to by TBPTR.”

14.6.3, 14-120

Between the second and third paragraph, add the following:

“The status field of the BD is 16-bit field, as is the length field. The data

buffer pointer is a 32-bit field. Therefore, the BDs should be accessed with

the following C structure:

typedef unsigned short uint_16; /* choose 16-bit native type */

typedef unsigned int uint_32; /* choose 32-bit native type */

typedef struct bd_struct {

uint_16 flags;

uint_16 length;

uint_32 bufptr;

};”

MPC8540 Datasheet(PDF) 1237 Page - Freescale Semiconductor, Inc