MPC8540 datasheet(1238/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-26

Freescale Semiconductor

Revision History

14.6.3.2, 14-124

In Table 14-120, change the LG bitfield description to read as follows:

“Rx frame length violation. Written by TSEC. (Only valid if L is set.) A

frame length greater than maximum frame length was recognized while

MACCFG2[HUGE FRAME] was set. Note, if MACCFG2[HUGE

FRAME] is cleared, the frame is truncated to the value programmed in the

Maximum Frame Length register.”

14.6.4, 14-125

Change the first paragraph to read:

“Some applications require the ability to identify selected portions of data

within a frame’s data payload. This process is called extraction, although

the data is not truly removed. Rather than literarily extracting a section of

the data and copying it into a new memory location, the data is placed in the

L2 cache. This allows the processor to quickly access critical frame

information as soon as the processor is ready without having to first fetch

the data from main memory. This results in substantial improvement in

throughput and hence reduction in latency.”

14.7.1.1, 14-129

n Table 14-123, add the following step immediately following the optional

DMACTRL initialization step:

14.7.1.2, 14-129

Change the title of Table 14-124 to read “GMII Interface Mode Signal

Configuration.”

14.7.1.2, 14-129

In Table 14-124, remove the TX_CLK signal from the list of GMII interface

signals and reduce the total number of signals listed at the bottom to 22.

14.7.1.2, 14-132

In Table 14-126, add the following step immediately following the optional

DMACTRL initialization step:

14.7.1.3, 14-136

In Table 14-129, add the following step immediately following the optional

DMACTRL initialization step:

14.7.1.4, 14-137

Change the title of Table 14–130 to read “RGMII Interface Mode Signal

Configuration.”

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

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