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MPC8540 Datasheet(PDF) 1240 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1240 Page - Freescale Semiconductor, Inc |
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1240 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 A-28 Freescale Semiconductor Revision History maintenance transactions,” reflecting the fact that any single DARn register can assume one of two formats. 15.3.2.10, 15-22 In Figure15-17, correct the offset value for CLSDAR2 to 0x2_1234. 15.3.2.11, 15-23 In Figure15-18, correct the offset value for the NLSDARn–DMA 2 next list descriptor address register to 0x2_123C. 15.5.1.1.1, 15-27 Change step 1 in the sequence to read, “Poll the channel state (see Table 15-21 "Channel State Table") to confirm that the specific DMA channel is idle.” 15.5.1.1.2, 15-28 Change step 1 in the sequence to read, “Poll the channel state (see Table 15-21 "Channel State Table") to confirm that the specific DMA channel is idle.” 15.5.1.1.3, 15-29 Change step 2 in the sequence to read, “Poll the channel state (see Table 15-21 "Channel State Table") to confirm that the specific DMA channel is idle.” 15.5.1.1.4, 15-29 Change step 3 in the sequence to read, “Poll the channel state (see Table 15-21 "Channel State Table") to confirm that the specific DMA channel is idle.” 15.5.1.2.3, 15-30 Change step 2 in the sequence to read, “Poll the channel state (see Table 15-21 "Channel State Table") to confirm that the specific DMA channel is idle.” 15.5.1.2.4, 15-31 Change step 3 in the sequence to read, “Poll the channel state (see Table 15-21 "Channel State Table") to confirm that the specific DMA channel is idle.” 15.4.1.3, 15-32 Replace Figure 15-22 with the following, showing more flexible negation of DREQ: DREQ CLOCK DACK DDONE Transfer Start Transfer In Progress Transfer Done Transfer Start Transfer Pause Transfer Restart EMP_EN |
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