MPC8540 datasheet(1243/1302 Pages) FREESCALE

1243 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-31

error actions. Likewise, some errors are enabled by programming two

bits—one in the PCI bus command register and another in the PCI/X error

enable register (ERR_EN).”

16.3.2.9, 16-40

In Figure 16-35, change the reset value from “0000_0000” to “0000_0000

(PCI); 0000_1000 (PCI-X)”.

16.3.2.19, 16-47

In Table 16-46, change the description for bit 0 to read as follows:

“PCI agent/host. Read-only. Indicates the reset value of the PCI host/agent

configuration signal, LWE3.

PCI interface is in host mode

PCI interface is in agent mode”

16.4.1, 16-51

Replace the second and third sentences of the third paragraph with the

following:

“The state of the reset signal is reflected in bit 15 (read-only) of the PCI bus

arbitration control register (PBACR[PAD]). Note that PAD is the inverse of

the arbiter configuration signal; that is, when PAD = 0 the arbiter is enabled,

and when PAD = 1 the arbiter is disabled.”

16.4.1.3, 16-53

Add the following to the end of the first paragraph:

“Note that the PCI-X bus arbiter does not support the broken master lockout

function.”

16.4.2.11.1, 16-69

Insert the following between the first and second sentences in the first

paragraph:

“Note that the Bus Master bit in the MPC8540’s PCI bus command register

must be set before an outbound configuration access is attempted.”

16.4.2.11.2–16.4.2.11.3, 16-69–16-71

Replace the existing sections with the following:

16.4.2.11.2 Accessing the PCI Configuration Space in Host Mode

To access the configuration space, a 32-bit value must be written to the PCI

CFG_ADDR register that specifies the target PCI bus, the target device on

that bus, and the configuration register to be accessed within that device.

Note that the Bus Master bit in the MPC8540’s PCI bus command register

must be set before an outbound configuration access is attempted. Device 0

on PCI/X bus 0 is the MPC8540 itself; thus, device 0, bus 0 is used to access

the internal PCI/X configuration header.

When the MPC8540 detects an access to PCI CFG_DATA, it checks the

enable flag and the device number in the PCI CFG_ADDR register. If the

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