MPC8540 datasheet(1239/1302 Pages) FREESCALE

1239 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-27

14.7.1.4, 14-140

In Table 14-132, add the following step immediately following the optional

DMACTRL initialization step:

14.7.1.5, 14-144

In Table 14-135, add the following step immediately following the optional

DMACTRL initialization step:

Chapter 15

Correct the DMA signal enumeration for consistency as in the following

example:

“DMA0_DREQ” to “DMA_DREQ0”

15.2.2, 15-5 and

15.4.1.3, 15-32

In the third bullet of the list of signals defined for the external control

interface, clarify that the falling edge of DMA_DREQ sets MRn[CS] and

for DMA_DDONE with the following:

“DMA_DDONE assertion indicates that the DMA engine has completed

the transfer. SRn[CB] is clear. Note, however, that write data may still be

queued at the target interface or in the process of transfer on an external

interface.”

15.3.1, 15-7

In Table 15-4, designate the following memory locations as “Reserved”:

0x2_112C

0x2_1148–0x2_117C

0x2_11AC

0x2_11C8–0x2_11FC

0x2_122C

0x2_1248–0x2_127C

0x2_12AC

0x2_12C8–0x2_12FC

15.3.2.5.1, 15-17

Change the designation for the source address register when used for

RapidIO maintenance transactions from “SARMn” to “SARn for RapidIO

maintenance transactions,” reflecting the fact that any single SARn register

can assume one of two formats.

15.3.2.7.1, 15-20

Change the designation for the destination address register when used for

RapidIO maintenance transactions from “DARMn” to “DARn for RapidIO

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

MPC8540 Datasheet(PDF) 1239 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1239 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL