MPC8540 datasheet(1241/1302 Pages) FREESCALE

1241 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-29

15.5.1.2, 15-42

Remove the last sentence of the second paragraph.

16.2, 16-12

In Table 16-2, add the following to the timing description for the PCI_PERR

signal:

“Note: If a parity error occurs on the last data beat of a PCI-X transaction

with inbound data (outbound read with split completion data or inbound

write), the MPC8540 asserts PERR longer than permitted by the PCI-X

specification. This condition may cause a subsequent transaction to

erroneously detect a parity error. The condition may be remedied by placing

a stronger pull-up resistors on the PERR signal. For example:

•1 Kohm for 133 MHz point-to-point operation

•2 Kohm for 66 MHz operation

•4 Kohm for 33 MHz operation.

These values are stronger than the specification allows (5 Kohm minimum

for pull-up resistors).”

16.3.1.2, 16-20

Add the following sentence to the end of the third paragraph:

“Note that outbound translation windows must not overlap the

configuration access registers.”

16.3.1.2.4, 16-22

In Figure 16–9, add a footnote to EN field (bit 0) that states, “ For

POWAR0, translation is always enabled. The enable field (EN) may be read

and written, but the value is ignored.”

16.3.1.2.4, 16-22

In Table 16–10, add the following to the description for bit 0 (EN), “Note

that for POWAR0, translation is always enabled. The enable field (EN) may

be read and written, but the value is ignored.”

16.3.1.2.4, 16–23

In Table 16–10, add the following to the description for bits 26–31 (OWS),

“Also note that for POWAR0, setting OWS to less than 4 Gbytes causes

addresses that miss in the other outbound windows to be aliased to the

smaller address range defined by POWAR0[OWS] and POTAR0.”

16.3.1.4, 16–27

Insert the following between the second and third paragraphs:

“Note that some errors are reported in two bits—one in the PCI/X error

detect register (ERR_DR) and another in the PCI bus status register in the

PCI/X configuration header. These bits must be cleared separately; that is,

clearing one does not clear the other. For example, clearing the

ERR_DR[Mstr abort error] does not clear the received master abort bit in

the PCI bus status register. In these cases, both bits must be cleared before

further error reporting can occur. Refer to Table 16-57 for PCI mode error

actions and Table 16-64 for PCI-X mode error actions. Likewise, some

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